1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a dynamic random access memory (DRAM) having an improved transistor structure.
2. Description of the Related Art
The integration density of a semiconductor integrated circuit such as a DRAM having MOS transistors becomes higher with the development of the semiconductor technology. With an increase in the integration density, the dimensions of MOS transistors constructing the integrated circuit are reduced into the sub-micron range. However, when it is required to further enhance the integration density, the following problems occur in the conventional MOS transistor and the further improvement in the integration density is limited.
The first problem is that it becomes difficult to suppress the leak current since the threshold voltage is reduced by a so-called "short channel effect" and the punch-through occurs when the gate length is reduced with miniaturization.
The second problem is that it is required to provide a mask alignment tolerance between a wiring contact for the source/drain and a gate electrode and between the contact and the element isolation area in order to stably form the wiring contact, thereby making it difficult to attain satisfactory miniaturization.
The third problem is that the sufficient surface flatness cannot be attained because of a step difference caused by formation of the gate electrode and it becomes difficult to form another wiring layer such as a bit line on the surface.
A NAND type DRAM memory cell structure in which a plurality of MOS transistors are series-connected and information storage capacitors are connected to the respective sources (or drains) of the MOS transistors is known in the art. Since, in the above series-connected type array system, the number of contacts with the bit lines can be reduced in comparison with a system other than the series-connected type array system, the cell area can be reduced.
However, the cell structure of a series-connected type array system has the following problem. That is, since a cell used in this case is a stacked type cell having a stacked capacitor and the cell area is small, it is required to form a capacitor with large height in order to attain necessary storage capacitance (Cs). As a result, an extremely large step difference of 1 .mu.m or more is formed on the substrate structure used when an upper wiring layer such as a bit line is formed and it becomes extremely difficult to form the upper wiring layer.
With the above condition taken into consideration, a so-called concave type MOS transistor, that is, a MOS transistor having a groove formed in the channel portion to increase the effective channel length, is expected as a transistor to be further miniaturized. Since it is difficult to miniaturize the concave type transistor when the conventional LOCOS isolation is used, the element isolation by trench isolation is used in the concave type transistor.
However, since the channel is formed along the groove surface of the trench in the concave type MOS transistor, the following problem occurs. That is, since the electric field from the gate electrode for controlling the channel formation is diverged in the bottom corner portion of the trench because of the shape thereof, a channel with high conductivity cannot be formed in this portion. As a result, the channel resistance increases and a sufficiently large driving ability cannot be attained.